Within the realm of semiconductor manufacturing technology, the trend toward ever-increasing device density, accompanied by corresponding decreases in device dimensions, seems unlikely to abate in the foreseeable future. Since the late 1960's, a new generation of integrated dynamic random access memory circuits has been developed approximately every four years. Each generation has been characterized by roughly a thirty percent reduction in device dimensions, which has resulted in a two to four-fold density increase over the previous generation.
In order to achieve the aforementioned density increases in dynamic random access memory arrays, circuit designers have had to confront two persistent challenges: that of maintaining adequate memory cell capacitance (in spite of the decreasing wafer surface area available for each cell), and that of minimizing sub-threshold current leakage (brought about by decreasing device channel lengths). In order to maintain adequate cell capacitance, circuit designers have largely forsaken planar cell capacitors, and are relying on increasingly complex, three-dimensional structures to provide additional plate area. In addition, silicon dioxide cell dielectric layers have been displaced by materials which have higher dielectric constants, (e.g., silicon nitride, tantalum pentoxide, and certain ferroelectric compounds). The problem of sub-threshold current leakage, on the other hand, has also been attacked in a number of ways, which will be explained with reference to FIG. 1.
FIG. 1 depicts plots on common axes of I.sub.DS (drain-to-source current) vs. V.sub.GS (gate voltage minus source voltage) for four representative devices. It should be pointed out that on none of the four plots does I.sub.DS start at zero, due to a certain amount of noise inherent in all circuits. The left-most plot A is characteristic of a relatively short-channel transistor, while the right-most plot D is characteristic of a relatively long-channel transistor. One technique that is now frequently used to reduce the short-channel effect is the implantation of an impurity of the opposite conductivity type used for the source and drain junctions as a halo surrounding the source and drain regions. The use of a punchthrough halo implant has the effect of shifting the entire curve from left to right and steepening the slope of the transition portion thereof. For example, a transistor with a somewhat short-channel effect and no punchthrough implant might produce a plot of I.sub.DS vs. V.sub.GS such as plot B of FIG. 1. The use of a punchthrough implant might result in a new plot similar to that of plot C. Another technique used to mitigate the short-channel effect is that of backbiasing the substrate with a charge pump to a negative potential. Backbiasing results in improved transistor shut-off characteristics, due to what is known as the transistor body effect. The transistor body effect tends to shift the V.sub.GS vs. I.sub.DS curve to the right and steepening the slope of its transition portion. Backbiasing of the substrate has its limitations. Due to the fact that V.sub.T (transistor threshold voltage) does not increase linearly with respect to negative increases in V.sub.BB due to transistor channel doping profile, one rapidly reaches the point of diminishing returns. Additionally, junction breakdown voltage is decreased through a backbiasing of the substrate. Consequently, substrate backbias voltages are typically no more negative than several volts. A third technique used to reduce the short-channel effect is the use of "smart sense amplifiers" on array bitlines. Such sense amps prevent the bitline from be pulled all the way to ground level during the period when a wordline is not activated, thereby decreasing both V.sub.GS and sub-threshold current leakage. However, as the bitline voltage is increased, signal strength suffers during read operations--especially in the case where charge has been stored within the cell capacitor. Consequently, the maximum pull-down voltage for bitlines used with smart sense amps is around 0.5 volts. The effect of increasing the bitline pull-down voltage is somewhat similar to the effect produced by the previously discussed techniques. Not only is the curve shifted to the right, but the "off" point on the curve is shifted down and to the left. For example, in the case of curve A (the plot showing an extreme short-channel effect), a rise in bitline pull-down voltage to 0.5 volts would result in a V.sub.GS value of -0.5 volts (point 11 on plot A). Although current flow has been reduced from the point where V.sub.GS is equal to zero (point 12 on plot A), significant subthreshold leakage would still occur, as the current flow level is far from the minimum value which corresponds to the average noise level value (represented by broken line 13). A fourth technique that is commonly used to reduce the short-channel effect is that of using a threshold voltage adjustment implant. For N-channel devices, boron is generally the preferred implant impurity. Once again, the use of this technique has its downside. As concentration of the V.sub.T adjustment implant increases, signal strength suffers during read operations as the voltage differential between the capacitor plates decreases as the V.sub.T adjustment implant concentration increases.
What is needed is an additional technique for reducing short-channel effect that does not hamper transistor or array function, which can be easily implemented given presently-available array architectures, and which can be used in combination with the techniques for mitigating short-channel effect that have been heretofore described.